Exemplary embodiments of the present invention relate to a setting circuit and integrated circuit including the same.
A synchronous semiconductor memory device uses a mode register and a mode register set (MRS). The mode register is a device in which data for controlling various operation modes of the synchronous memory device is programmed and stored.
A central processing unit (CPU) accesses a synchronous semiconductor memory device in such a state that operation modes, such as a column address strobe latency (CL) or a column address strobe write latency (CWL), are previously set. Such a set operation mode is stored in mode registers, and a series of mode registers is referred to as a mode register set.
A series of codes representing the modes of the integrated circuit are set in the mode register set, and such codes are referred to an MRS code.
FIG. 1 is a diagram of a conventional setting circuit.
Referring to FIG. 1, the setting circuit includes a command decoding unit 110 and a setting information generation unit 120. The command decoding unit 110 is configured to activate a read signal RD, a write signal WT, and an MRS signal MRS in response to a command CMD and an address ADD. The setting information generation unit 120 is configured to generate setting information SET_INF in response to the address ADD when the MRS signal MRS is activated. The read signal RD is a signal applied when reading data from an integrated circuit, and the write signal WT is a signal applied when writing data to the integrated circuit.
The integrated circuit performs a test operation for testing operations under various environments, as well as general operations. In this case, in order to operate in other modes, the setting information generation unit 120 receives the address ADD and generates different setting information SET_IN.
An address input unit (not shown) receives the address ADD from the outside of the chip. Therefore, when the address ADD is received, a current flowing through the inside of the integrated circuit increases. In particular, in the case of a test operation which is frequently used, if the address ADD is received and the setting information SET_INF is generated in every test operation, a current flowing through the inside of the integrated circuit increases.